Apparatus and method for co-simulating processors and DUT modules

ABSTRACT

An apparatus and method for co-simulating of processors and DUT modules comprising steps of constructing and executing a processor simulation program and a Hardware Description Language (HDL) simulation environment that is activated by a corresponding simulator, and further for executing a command processing model and the processor simulation program, and establishing a message queue as a buffer of the message and data. Whenever the intercommunication occurred, the command will be processed via a Program Language Interface (PLI), the command processing model, a message queue mechanism for I/O command, and a signal mechanism for interrupt command.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to the field of simulation, and more particularly to an apparatus and a method for co-simulating processors and DUT modules.

2. Description of the Related Art

For a long time, designers of the digital design field employing the hardware description language (HDL) such as Verilog and VHDL as tools for modeling the concurrency processes of hardware elements in the digital circuits and for simulation of the system-level designs. A common approach is to design each IC chip, use an HDL, and then verify system functionality via simulation. In general, digital circuits are modeled as sets of modules, described at a register transfer level (RTL) by use of a HDL, and designer had to specify how the data flow between registers and how the design processes the data. Moreover, designer aims to verify the whole design under test (DUT) modules should construct a processor model and create corresponding programming language interface (PLI) library to perform the simulation.

With regard to the above-mentioned, FIG. 1A is a flowchart illustrating the method for the processor simulation based on the related art comprising steps of constructing a processor model in a HDL in step 100 to simulate the intercommunication between the processor (or a micro-controller unit; MCU) and the DUT modules, and then the processor model performing the simulation process in step 110. Moreover, FIG. 1B is a flowchart illustrating the details of the processor model performing the simulation process based on the related art, and the step 110 comprising of linking and binding the code of the processor model so as to append the processor model as a function of the PLI library namely a PLI task in accordance with the command of the PLI in step 111, and starting a simulator for performing the PLI task and the RTL code to complete the simulation in step 112.

However, the method for the processor simulation based on the related art has some drawbacks. First, a processor model created in a HDL needs to describe the layout and the relations between all the components as exhaustively as possible, and it increases the complexity in the processor model developing stage and seems to waste much time and laboriously to create a processor model for simulation. Second, it costs a great deal of simulation time to verify the DUT models functionality in the simulating stage. That is, one of the cruxes of the problem is that the testing staff should wait for a long time to obtain the simulation result since the processor model perform the RTL code in the simulation process, and the inner operations and the status transition of the processor seems to be unconcerned for the staff in the co-simulation processes of the processor and the DUT modules. Furthermore, the other crux of the problem is that since the engineer should develop the special purpose code applied to the specific DUT module as a testbench and hence create the PLI task for simulation, it seems lacking of reusability and efficiency.

SUMMARY OF THE INVENTION

The present invention provides an apparatus for co-simulating processors and DUT modules comprising a Hardware Description Language (HDL) simulation environment for providing a performing environment for at least a DUT module coupled to at least a processor, wherein the HDL simulation environment constructed in a HDL and performed by a simulator; a processor simulation program for simulating functions of the processor, wherein said processor simulation program constructed in a programming language differs from the HDL; and at least a DUT module for interacting with the processor simulation program, wherein the DUT module constructed in the HDL, and indicating the peripheral devices coupled to the processor.

The present invention also provides a method for co-simulating processors and DUT modules comprising steps of constructing and performing a HDL simulation environment constructed in a Hardware Description Language, constructing a processor simulation program in a programming language differs from the Hardware Description Language, constructing a DUT module in the Hardware Description Language, and performing the processor simulation program and the DUT model for simulating the co-simulation of processors and DUT modules.

The present invention further provides a method for verifying a design of a peripheral device comprising steps of constructing a processor simulation program in a first program language; constructing a interface model program in a second program language differs from the first program language, wherein the second program language is a hardware description language; constructing a peripheral device program in the second program language; and performing the interface model program for simulating a interaction of processors and the peripheral device in a workstation platform.

Consequently, the present invention improves efficiency, reduces cost of the development, and simplifies the simulation procedures and complexity.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects, features, and advantages of the present invention will become better understood with regard to the following description, and accompanying drawings where:

FIG. 1A is a flowchart illustrating the method for the processor simulation based on the related art;

FIG. 1B is a flowchart illustrating the details of the processor model performing the simulation process based on the related art;

FIG. 2A is a schematic diagram illustrating the apparatus for co-simulating processors and DUT modules based on an embodiment of the present invention;

FIG. 2B is a schematic diagram illustrating the apparatus for co-simulating processors and DUT modules based on another embodiment of the present invention;

FIG. 3A is a flowchart illustrating the details of the processor model performing the simulation based on the other embodiment of the present invention; and

FIG. 3B is a schematic diagram illustrating the co-simulation of a RISC processor and a DUT module based on the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 2A is a schematic diagram illustrating the apparatus for co-simulating processors and DUT modules based on an embodiment of the present invention, and it comprising a processor simulation program 200 coded in C language (e.g. GNU C) and hence as a function of API library after compiled, and a HDL simulation environment 210. It's noted that these two programs performing their code independent till the intercommunication occurred such as an I/O request and corresponding acknowledge, and an interrupt request, etc., and then the corresponding command and message will be issued and exchanged to complete the process.

FIG. 2B is a schematic diagram illustrating the apparatus for co-simulating processors and DUT modules based on another embodiment of the present invention comprising a processor simulation program 200 and a HDL simulation environment 210, wherein the HDL simulation environment 210 further comprising a PLI 211 which is a library of a HDL that the build-in function can be taken by a processor simulation program 200 and a command processing model 212 for accessing a message queue and generated the corresponding hardware control signal; a command processing model 212 coded and compiled in a HDL and a compiler to simulate the access process of the processor and the peripheral such as a system bus; and a DUT modules 213 comprising the peripheral that under testing and coupled to the processor such as a MCU, a DSP and a RISC processor. Consider the co-simulation of various types of processors and DUT modules, the corresponding codes of the peripheral will be appended to the original processor simulation program 200, and the command processing model 212 be constructed in HDL as a whole.

FIG. 3A is a flowchart illustrating the details of the processor model performing the simulation based on the other embodiment of the present invention comprising steps of constructing and performing a HDL simulation environment 210 constructed in a HDL such as Verilog or VHDL, and then performed the simulation by a simulator such as Verilog-XL or NC-Verilog in a platform such as a workstation running the Unix operation system among the command processing model 212, the PLI 211, and the DUT modules 213 in step 300. On the other hand, the processor simulation program 200 constructed in step 310 and performed in step 320 comprising of constructing a message queue for buffering the command and message and generating a process identification number. Subsequently, proceeding the intercommunication of the processor simulation program 200 and the HDL simulation environment 210 in step 330. For instance, when the processor simulation program 200 issues the I/O request command to peripheral or receives the corresponding acknowledge signal issued by the peripheral, it can access the message queue through the PLI built-in the HDL simulation environment, and the command converted into the hardware control signal to drive the peripheral to retrieve data, and return the result to the command sender. Besides, when an interrupt command issued by the peripheral, the processor and the command processing model 212 will call the interrupt service routine (ISR) of the processor simulation program 200 to process the interrupt command via the function “signal” of the Unix operation system.

Furthermore, FIG. 3B is a schematic diagram illustrating the co-simulation of a RISC processor and a DUT module based on the present invention. When a processor simulation program “RISC.C” 340 constructed in C language generating an I/O command such as accessing the memory for retrieving required data, it loading a header file “RISCCmd.h” 341 and utilizing the function “SendCmd” to transmit and store the command, address, and data to the message queue 342, and the Verilog PLI “libpli.so” 351 will access the message queue 342 to read the message via function “GetRISCCmd” and then converted into the hardware control signal to a system bus interface model “RiscBus.mdl” 352 and further to access memory by a memory decoder 353, and then the corresponding acknowledge signal will be issued via function “PutRISCAck” and stored in the message queue 342 by the Verilog PLI “libpli.so” 351 for the processor simulation program “RISC.C” 340 to retrieve via function ReceiveAck.

The above discussion on the techniques of present invention has at least two advantages. First, utilizing the concept of modulization for reducing the difficulty in model construction, simplifying the complexity of the model, and decreasing the cost of developing the simulation program. In other words, the present invention construct a processor simulation program and a HDL simulation environment model instead of construct a whole processor model, the former task seems relatively simple than the later one. Second, The processor simulation program of the present invention has some characters such as time-saving that caused by avoiding to perform the CPU RTL code, device-independent, reusability, portability, usability, etc., since it's not construct for testing and simulating specific peripheral devices. Besides, the initiative and the two-way message passing can be achieved via performing the co-simulating procedures of the processor simulation program and the DUT modules in a common HDL environment, and using corresponding mechanism provided by the system.

While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention need not be limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit of appended claims, the scope of which should be accorded the broadest interpretation so as to encompass all such modifications and similar structures. 

1. An apparatus for co-simulating of processors and DUT modules comprising: a Hardware Description Language (HDL) simulation environment for providing a performing environment for at least a DUT module coupled to at least a processor, wherein said HDL simulation environment constructed in a HDL and performed by a simulator; at least a processor simulation program for simulating functions of said processors, wherein said processor simulation program constructed in a programming language differs from said HDL; and a DUT module for interacting with said processor simulation program, wherein said DUT module constructed in said HDL and indicating the peripheral devices coupled to said processor.
 2. The apparatus as recited in claim 1, further comprising: a compiler for compiling said processor simulation program, wherein said compiler installed in a same platform of said processor simulation program.
 3. The apparatus as recited in claim 2, wherein said same platform is an Unix-like workstation.
 4. The apparatus as recited in claim 1, further comprising: a process number for identifying processes under a multi-processor and a multi-task architecture; and a message queue for storing the messages of co-simulating of processors and DUT modules.
 5. The apparatus as recited in claim 1, wherein said HDL simulation environment further comprising: a command processing model for providing a interface to process interaction of said processor simulation program and said DUT module.
 6. The apparatus as recited in claim 5, wherein said HDL selected form the group consisting of Verilog and VHDL.
 7. The apparatus as recited in claim 5, wherein said HDL simulation environment further comprising: a Programming Language Interface (PLI) for providing a library for function call from said HDL simulation environment and said processor simulation program.
 8. The apparatus as recited in claim 1, wherein said simulator selected form the group consisting of Verilog-XL and NC-Verilog.
 9. A method for co-simulating of processors and DUT modules comprising: constructing and performing a HDL simulation environment constructed in a HDL; constructing a processor simulation program in a programming language differs from said HDL; constructing a DUT module in said HDL; and performing said processor simulation program and said DUT model for simulating processors and DUT modules.
 10. The method as recited in claim 9, further comprising: generating a process number for identifying processes under a multi-processor and a multi-task architecture.
 11. The method as recited in claim 9, further comprising: utilizing a library of a PLI provided by said HDL and a message queue mechanism to perform and access messages; and utilizing said library and a signal mechanism to process the interrupt messages.
 12. The method as recited in claim 9, wherein said processor simulation program and said DUT model is performed in a same platform of Unix-like workstation.
 13. The method as recited in claim 9, further comprising: constructing a command processing model for providing a interface to process interaction of said processor simulation program and said DUT module.
 14. A method for verifying a design of a peripheral device comprising: constructing a processor simulation program in a first program language; constructing an interface model program in a second program language differs from said first program language, wherein said second program language is a HDL; constructing a peripheral device program in said second program language; and performing said interface model program for simulating interaction of processors and said peripheral device in a workstation platform. 